Debug support for RISC-V core IP and silicon

November 13, 2017 //By Graham Prophet
Development tool vendor Lauterbach, and SiFive, fabless provider of customised, open-source-enabled semiconductors, have announced that Lauterbach’s TRACE32 toolset will provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA.

Founded by the creators of RISC-V, SiFive IP sets out to contain the increasing cost of designing and manufacturing new chip architectures, “democratising access to custom silicon”. SiFive claims more public customers and working silicon in the market than any other RISC-V vendor.

This architecture joins products from more than 75 silicon companies supported by Lauterbach’s TRACE32 debug tools that promise to aid development of robust code whilst minimising time lost to debugging.

Lauterbach TRACE32 provides multicore debugging on individual hardware threads of SiFive cores, enabling debugging right from the reset vector, which analyses startup codes and other key functions. Lauterbach also provides high-level and assembler debugging for a variety of standard ISA extensions, such as compressed instructions and floating point. It also fully supports the JTAG Debug Transport Module (DTM) in all SiFive chips, and has planned support for other debug interfaces such as USB.

Lauterbach; www.lauterbach.com

 

SiFive; www.sifive.com